Solid-state image sensors offering low readout noise, high sensitivity and high dynamic range are devices of major interest in many fields such as digital consumer cameras, machine vision, life science imaging applications and night vision systems.
Reduction of electronic readout noise in Complementary Metal Oxide Semiconductor (CMOS) image sensors relying on conventional architectures, especially those operated at standard video frame rates or those optimized for still picture acquisition requires high values of capacitances for the implementation of necessary low-pass filters with particularly low bandwidth. Manufacturing of these capacitances demands significant silicon area and therefore results in increased device cost and larger chip area.
With reference to FIG. 1 a prior art image sensor 100 includes a matrix of pixel circuits 110 and a number of column signal lines 120. Each pixel circuit 110 includes a photo-sensitive device 111, such as a buried photodiode with a transfer gate, a photogate, a charge coupled device (CCD) or a p-n-photodiode, a source-follower transistor 113, a reset transistor 114, a select transistor 115, and a sense node capacitor 116 which may be implemented as a parasitic capacitance. Various elements such as source-follower transistor 113 and/or sense node capacitor 116 may be shared among neighbouring pixels in order to reduce transistor count. Depending on the selection of shared elements and the number of pixels sharing a given element, such pixels are for example referred to as 1.25-T, 1.5-T, 1.75-T or 2T pixels. Image sensor 100 further includes a low-pass filter (LPF) 190 and a current source 140 which are connected to every column signal line 120. LPF 190 and/or current source 140 may also be shared with a plurality of pixel circuits 110. A sample-and-hold (S/H) circuit 130 is connected to the output of each LPF 190.
A row decoder 102 generates the control signals for reset transistors 114 and select switches 115 of each pixel circuit 110. A common reset voltage grid 170 is connected to all pixel circuits 110 of the matrix.
During the readout of a given pixel circuit 110, reset transistor 114, the transfer gate of photo-sensitive device 111 if implemented by a buried photodiode, as well as the controls of S/H circuit 130 are operated in a manner which allows consecutive sampling of the reset value and the signal value and holding of the two values on the output of S/H circuit 130.
During both sampling processes, thermal noise generated in the channel of source-follower transistor 113 is sampled and held by S/H circuit 130. Further electronic circuits or software may be used for subtracting the sampled reset value from the signal value for cancellation of pixel reset noise and the offset of source-follower transistor 113. This subtraction process is commonly referred to as correlated double sampling (CDS). Since the thermal noise components of the signal value and the reset value held by S/H circuit 130 are not sampled simultaneously, they are not correlated. Therefore, the thermal noise of source-follower transistor 113 and current source 140 is not cancelled by CDS and the statistical variation of the thermal noise voltage is increased by a factor of sqrt(2) when determining a difference of two samples.
The application of low-pass filtering has been shown to be an adequate method for controlling thermal noise of image sensors, as taught for example in European Patent EP1643754 (Seitz et al.). The task of low-pass filtering is accomplished by LPF 190. A possible implementation of this approach is achieved by using the natural LPF characteristics of the capacitance-loaded source-follower buffer setup including a source-follower transistor 113, current source 140, and a load capacitor 191 for low-pass filtering. In this case the input and output node of low-pass-filter 190 are identical. The load capacitance of the source follower buffer setup includes the parasitic capacitance of column signal line 120, the capacitance of load capacitor 191, and the input capacitance of S/H circuit 130. S/H circuit 130 include at least one sampling switch (not shown) and a sampling capacitor (not shown) for the reset value as well as for the signal value. In some cases, the sampling capacitors may take the role of low-pass filtering load capacitors 191 if their dimensions, and thus the corresponding capacitances, are chosen large enough. The thermal noise level is controlled by proper choice of the capacitance load of the source-follower transistor 113. In practical designs it is usually possible to reduce the thermal noise contributed by current source 140 to an amount significantly below the thermal noise contributed by source-follower transistor 113. The thermal noise contained in either the reset value or the signal value can therefore be approximated by the thermal noise of source-follower transistor 113, as given by the following equation (EQN) 1:
                              q                      sn            ,            thermal            ,            conventional                          ≈                              C                          sn              ,              conventional                                ⁢                                                    γ                ⁢                                                                  ⁢                kT                                            C                                  load                  ,                  conventional                                                                                        (        1        )            wherein qsn,thermal,conventional is the root-mean-square (RMS) of the equivalent noise charge (ENC) at a sense node 117 to the thermal noise contained in the reset value or the signal value, Csn,conventional is the capacitance of sense node capacitor 116, Cload,conventional is the overall capacitance of column signal line 120 while sampling the reset value or signal value, k is the Boltzmann constant, T is the absolute temperature, and γ is the thermal noise excess factor of a MOS transistor.
For currently used semiconductor manufacturing technologies it is reasonable to assume, for example, a value of 2 for γ and a value of 5 femto-Farads for Csn,conventional. For ultra-low-noise sensors with overall RMS noise of the order of one electron, thermal noise from source-follower transistor 113 and current source 140 should not exceed the value of about 0.5 electrons at room temperature. From EQN 1 and the assumed values it becomes apparent that Cload, conventional needs to take a value of, for example, 66 pico-Farads in order to achieve this requirement for the difference value, determined by CDS. If the majority of load capacitance is contributed by the sampling capacitors used in S/H circuit 130, or otherwise stated, capacitances of the sampling capacitors are larger than another capacitance like e.g. parasitic capacitance of column signal line 120 and/or of a dedicated additional low-pass filtering load capacitor 191, and equal capacitance values are used for the sampling capacitors of the reset value and signal value sampling, the sum of the capacitance required per column signal line 120 is as high as 132 pico-Farads in the considered example. If a state-of-the art CMOS manufacturing process is used, a limited capacitance density, as for example 5 femto-Farads per μm2, can be achieved. The area of the capacitors needed to attain the required capacitance per column signal line would therefore be as high as 5 mm by 5 μm, which means that the area used by the capacitors is of an order of magnitude comparable to the area of the pixel array. Ultra-low-noise CMOS image sensors based on the described architecture can therefore not be produced at competitive package size and manufacturing cost.
A further limitation of the prior art image sensor architecture, as depicted in FIG. 1, is the fact that the conversion factor between signal charge and the voltage difference of the reset and signal values sampled by S/H circuit 130 is mainly defined by the value of sense node capacitance Csn as the signal chain does not employ or provide any voltage amplification.
Image sensors with a column circuit employing an inverting capacitance feedback amplifier have been proposed, for example by Krymski et al. (A 2e noise 1.3 Megapixel Sensor, in Proc. 2003 IEEE Workshop on CCDs and Advanced Image Sensors, Bruges, Belgium, May 15-17, 2003). These column circuits include an amplifier, an input capacitance coupling the column signal to a virtual ground node of the amplifier, and a feedback capacitance connected between the virtual ground node and the amplifier output. By resetting the charge of the feedback capacitance while the column line voltage corresponds to the reset level, the switched capacitor amplifier will perform subtraction of the reset level and the signal level as soon as the signal level is provided on the column signal line. Such a column circuit thus provides embedded CDS functionality. Furthermore, this architecture of column circuit may provide voltage amplification if the ratio of the feedback capacitance over the input capacitance is suitably chosen. The described switched capacitor amplifier based column circuit, however, does not perform perfect low-pass filtering of the processed column line signal, because the small signal transfer function of the described column circuit contains, besides the dominant pole at low frequency, a zero. As is known in the art, the term “small signal transfer function” refers to the frequency dependent input-to-output characteristics for signals that are small enough to allow linear approximation of the circuit behaviour. The small signal transfer function thus has a constant frequency response beyond the complex frequency of the zero rather than increasing attenuation. For this reason, to achieve effective suppression of high-frequency components of thermal noise, the employment of a large filtering capacitor connected to the column signal line would be needed nevertheless. Furthermore, the transistors included in the amplifier of this column circuit contribute additional thermal noise to the processed column line signal. This thermal noise contribution may, depending on various design parameters, significantly deteriorate the overall noise performance of the sensor.